Machine Intelligence Research Labs (MIR Labs) - Global Network for Innovation and Research Excellence

Satish Chandra Tiwari
University Of Delhi, New Delhi
PhD Student
Personal Web Site:
Main page: http://www.mirlabs.net/global/index.php?c=main&a=person&id=605
Short Biography
Satish Chandra Tiwari received the B.Sc.and M.Sc. degree in electronics from University Of Delhi and Budenlkhand University respectively. He received the the M.Tech degree in VLSI design from Indraprastha University, New Delhi, in 2009.He currently is pursuing the Ph.D. degree in electronics engineering at the Division of ECE, NSIT, University of Delhi. From March 2009 to July 2009 he was an intern in IC Design Group, Cadence Design Systems, Noida, India, where he worked on generation and validation of test cases for Cadence Encounter. His research interests include low power high density digital circuits. He has more than seven publications in International journals/conferences. He has two patents pending with IPO.
List of top 5 publications in the last 5 years
Singh, K.; Tiwari, S.C.; Gupta, M.; , "Design and development of circuit optimizer using TCl and SPECTREMDL(SPICE) interface," Information and Communication Technologies (WICT), 2011 World Congress on , vol., no., pp.257-262, 11-14 Dec. 2011 Singh, K.; Tiwari, S.C.; Gupta, M.; , "A high performance flip flop for low power low voltage systems," Information and Communication Technologies (WICT), 2011 World Congress on , vol., no., pp.257-262, 11-14 Dec. 2011 doi: 10.1109/WICT.2011.6141254 Tiwari, S.C.; Singh, K.; Gupta, M.; , "A novel methodology for flip-flop optimization and characterization in NOC design space," Information and Communication Technologies (WICT), 2011 World Congress on , vol., no., pp.251-256, 11-14 Dec. 2011 doi: 10.1109/WICT.2011.6141253 Tiwari, S.C.; Gupta, A.; Singh, K.; Gupta, M.; , "Logical effort based automated transistor width optimization methodology," Information and Communication Technologies (WICT), 2011 World Congress on , vol., no., pp.1067-1072, 11-14 Dec. 2011 doi: 10.1109/WICT.2011.6141396 Tiwari, S.C.; Singh, K.; Gupta, M.; , "A Low Power High Density Double Edge Triggered Flip Flop for Low Voltage Systems," Advances in Recent Technologies in Communication and Computing (ARTCom), 2010 International Conference on , vol., no., pp.377-380, 16-17 Oct. 2010 doi: 10.1109/ARTCom.2010.64 Sharma, M.; Noor, A.; Tiwari, S.C.; Singh, K.; , "An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop," Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on , vol., no., pp.478-481, 27-28 Oct. 2009 doi: 10.1109/ARTCom.2009.207
List of top 5 academic activities during the last 5 years
Program committee member CICN and CSNT 2012. Program committee member WICT 2011. Mentored the development of Advance VLSI lab (CADENCE tools) 2010. Mentored the development of Advance VLSI lab ( MENTOR tools) 2011. Member of local organizing committee for ISTAM 2009..