Dr. Usha Sandeep Mehta

At a glance:

·       Sr. Associate Professor at PG VLSI design, EC Dept. Nirma University, Ahmedabad

·       Total Experience :15.5 years (Including : Academic: 10.5; Industrial: 4; Research: 1)

·       Joint Secretary for the 2^nd International Conference on Current Trends in Technology NUiCONE-2011 supported by IEEE

·       Nominated for the Shayesta Akhatar Memorial National Award for Best Woman Engineering College Teacher for year 2010 by Institute of Technology, Nirma University, Ahmedabad

·       Session Chair at IEEE Asia Pacific Conference on Circuit and Systems (APCCAS- 2010) at Kuala-Lumpur- Malaysia,

·       Program Committee Member at

§           The International Conference on Computational Intelligence and Communication Networks(CICN-2011), Gwalior-India

§           World Congress of Information and Communication Technologies (WICT-2011), supported by IEEE at Mumbai- India during December 11-14, 2011

§           International Conference on Soft Computing for Problem Solving (SOCPROS-2011), organized jointly by IEEE and  MIR labs at IIT, Roorkee, India during December 16-18, 2011

§           Nirma University International Conference on Emerging Trends of Technology (NUiCONE: 2011, 2010, and NUCONE : 2009 to 2006)

·       Reviewer for many national and international conferences and books

·       Organized ISTE approved, self financed Short Term training Programs and Workshops

·       Paper Setter for post graduate courses and Examiner Post Graduate dissertations at Master level thesis for North Maharashtra University, Gujarat Technical University, Hemachandracharya University, etc.

·       Reviewer of M. E. Dissertation at Gujarat Technological University.

·       Member of Board of Studies, Alumni Association, Editorial board for News letter etc.

·       More than 37 papers presented in peer reviewed and highly cited international journals and conferences.

·       Attended more than 30 conferences, workshops, seminars, symposiums, training programs etc.

·       Guided more than 30 post graduate dissertation at university including 25 post graduate dissertations in collaboration with industry.

·       Membership of various organization like IEEE, ISTE, VSI, CSI, IETE and IEI

·       Variety of Articles are published in various technical and non-technical magazines

1.                        “Weighted Transition Based Reordering, Columnwise Bit Filling and Difference Vector – A Power Aware Test Data Compression Method” in  Special Issue “CAD for Gigascale SoC Design and Verification Solutions” of International Journal “VLSI Design” by Hindawi Publications, Vol. 2011, Article ID : 756561

2.                        “Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead”, International Journal of Electronics Testing: Theory and Application (JETTA) from Springer Publication Corporation, Volume 26, Number 6, December 2011, Page No. 679-690. (26:679-688, DOI 10.1007/s10836-010-5183-6)

3.                        “Suitability of Various Low Power Testing Techniques for IP Core Based SoC: A Survey”, International Journal “VLSI Design” from Hindawi Publication Corporation

4.                    “2D Reordering: Optimization of Test Data Compression Method for Power and Time” is in press for International Journal of Electronics and Communication Engineering & Technology (IJECET), issue:  (July-Aug 2010)

5.                        “Run Length Based Test Data Compression Techniques: How Far From Entropy and Power Bounds?” is published in an open access International Journal “VLSI Design” from Hindawi Publication Corporation Volume 2010 Article ID 670476. (The impact factor of the journal is 0.211)

6.               “Object  Oriented Implementation of Combinational Controllability and Observability Algorithms” International  Journal of Electronics Engineering, Volume 2, Issue 1, January-June, 2010, (Page No. 93-97) 

7.                   “Development of Testability Guided ATPG Using the Reduced Fault Set” in International  Journal of Computational Intelligence Research & Application” Vol. 3  No. 1 January-June 2009,  (Page No. 131-137) 

1. Conference Chair, Nirma University International Conference On Engineering NUiCONE-2012 Organized in collaboration with IEEE
2. Conference Co-Chair, Nirma University International Conference On Engineering NUiCONE-2011 Organized in collaboration with IEEE 
3. An ISTE approved self finance one week Short Term Training Program on “Advances in Digital VLSI Design” from 21^st to 26^th June, 2010. Total 41 participants from various industries and institutes like NTPC, Apex Engg. Gandhinagar, Fr. Agnel Insti.of Tech., New Bombay, College of Engg, Ambajogar, Anna Saheb College of Engg. Sangali, H. G. College of Engg, Vahelal, B. V. M. Vidyanagar, L. C. I. T., Bhandu, M. S. Uni. Baroda, Nirma University, etc. actively participated in it.
4.  A self finance one day workshop on “Advance EDA Tools for VLSI Testing” on 28^th March 2009.
5.  An ISTE approved self finance one week Short Term Training Program on “Overview of VLSI Design and Technology” from 18^th to 23^rd December, 2006.