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| Anil Kumar Sahu |
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| CSVTU bhilai, Durg |
| Regular Member |
| Personal Web Site: https://anilsahu82.yolasite.com/About-ME.php |
| Main page: http://www.mirlabs.net/global/index.php?c=main&a=person&id=1538 |
| Short Biography |
| Mr. Anil Kumar Sahu is working as assistant professor in shrishankaracharya group of institutions, Bhilai,Chattisgarh in India. He ihas completed his Ph.D. From Swami Vivekananda technical university Bhilai. He has completed his M.Techin Microelectronics and VLSI Design from SGSIT, INDORE in(2008) . He has selected as a Research Associate in BITS Pilani in 2009.He has 10years of academic experience and has 45 international journal and 25 national Conference and international conference publications. Prof Sahu‘s area of interest isin the field of Mixed signal design ,VLSI testing ,a front end VLSI Design. |
| List of top 5 publications in the last 5 years |
[1] Sahu, A. K., Chandra, V. K., and Sinha, G. R. 2017. System Level Modeling and Simulation of Built-in-Self-Test Enable Oversampling Analog-to-Digital Converter. The Asian Journal of Convergence in Technology (AJCT) , ISSN No.:2350-1146, I.F 2.71 Volume III, Issue III,2017. https://doi.org/https://doi.org/10.1212/ajct.v3i3.316. [UGC Unpaid Journal] [2] Sahu A.K., Chandra V.K, and Sinha G. R.2017. Coordinate Rotation Digital Computer Enabled Built-in-Self-Test Scheme for Oversampling Analog-to-Digital Converter.Special Issue On Recent Knowledge in Engineering and Technology in International Journal of Pure and Applied Mathematics.117(15):465-477.ISSN No.: 1311-8080 (printed version); ISSN No.: 1314-3395 (on-line version). [Scopus Index and UGC Approve Journal]. http://acadpubl.eu/jsi/2017-117-15/issue15.html. [3]Sahu A.K., Chandra V.K, and Sinha G. R.2017.Modeling And Analysis Of Quantization Noise And Power Estimation Of Continuous-Time Delta Sigma Analog-To-Digital Converter Using Test Enable Feature For 4G Radios.Special Issue On Environment, Engineering & Energy in Journal of Advanced Research in Dynamical and Control Systems.9(14):1323-1333.ISSN No.: 1943-023X. [Scopus Index and UGC Approve Journal].http://www.jardcs.org/abstract.php?archiveid=1899. [4] Sahu A.K., Chandra V.K, and Sinha G. R.2018. Design Concept of Reduction of Chip Area Overhead and Power Consumptions of Single Loop CT Sigma Delta ADC Using BIST. 31 March 2018 Special Issue (Emerging Engineering Technologies Trends) in Journal of Engineering Technology. ISSN: 0747-9964. [Science Citation Index Expanded, Scopus Index and UGC Approve Journal]. [5] Sahu, A. K., Chandra, V. K., and Sinha, G. R. 2017. Optimized system level design and simulation analysis for characterization of performance of single loop CT sigma-delta modulators A/D . International Journal Of Engineering Sciences & Research Technology, 6(9): 249-254. ISSN No.: 2277-9655 . [UGC Journal] |
| List of top 5 academic activities during the last 5 years |
[1] Sahu A.K., Chandra V.K, and Sinha G. R.2017. Optimized System Level Modeling of CORDIC Enabled Built-in-Self-Test of Sigma-Delta Analogue-to-Digital Converter.2nd IEEE. International Conference for Convergence in Technology (I2CT)” Pune .[Available in IEEE Digital Library] [2] Sahu A.K., Chandra V.K, and Sinha G. R.2017.Modeling of Test Stimulus Generator for Characterization of Sigma-Delta A/D using MATLAB/ Simulink. All India Conference on Digital Technology in electrical and electronic Engineering CSIT Durg ,C.G ,India.(ISBN: 978-81-923288-5-0). [3] Sahu A.K., Chandra V.K, and Sinha G. R. 2017. High Level Computation Technique for Characterization of Sigma-Delta A/D Converter.IEEE International Conference on Microelectronics Devices, Circuits, and Systems (ICMDCS 2017) VIT University, Vellore, INDIA.1-4.doi:10.1109/ICMDCS.2017.8211601. [Available in IEEE Digital Library and also Scopus Indexed] [4]
Sahu A.K., Chandra V.K, and Sinha G. R.
2017. Design of Single-loop CT
Sigma-Delta Modulators for High Resolution -Wideband Applications Using GUI. IEEE International Conference on energy, Communication, Data Analytic and Soft
Computing (ICECDS 2017) .SKR Engineering College Nazarathpet ,Poonamallee,
Chennai Tamil Nadu [5] Sahu A.K., Chandra V.K, and Sinha G.R. 2017. Design of A Low Power Op-Amp-less ASDM using 45 nm BICMOS Technology to linearise VCO-ADC.IEEE International Conference on energy, Communication, Data Analytic and Soft Computing (ICECDS 2017) . SKR Engineering College Nazarathpet ,Poonamallee,ChennaiTamilNaduChennai, India .241-243.DOI: [Available in IEEE Digital Library] [6] Sahu A.K., Chandra V.K, and Sinha G. R.2017.Modeling and System Level Computer Simulation Approach for Optimization of Single Loop CT Sigma Delta ADC.The International Conference on Data and Information Sciences (ICDIS-2017) .Amerkantak M.P.17-18 November 2017. [Published in Springer Book Series "Lecture Notes in Networks and Systems”]. |